Multi-phase clock generators have been used in semiconductor integrated circuits for a variety of different applications. One common application of a multi-phase clock generator is in telecommunications equipment for capturing data received from high-speed Asynchronous Transfer Mode (ATM) Wide Area Networks (WAN) and Local Area Networks (LAN), for example. The phase of the input data is compared with each available phase output from the clock generator. The phase output that most closely matches the phase of the input data is selected to control latches which acquire the input data.
A typical multi-phase clock generator generates n pairs of clock signals which are equally distributed in phase over 360 degrees. An analog phase-locked loop (PLL) or ring oscillator is typically used to generate the clock signals. While analog PLLs can generate multiple clock signals that are substantially equally distributed in phase, these circuits have several disadvantages. For example if the reference clock input to the PLL stops, the PLL loses phase lock, which must be re-established when the reference clock returns. Also, analog PLL circuits are relatively sensitive to variations in process, voltage and temperature. Analog PLLs can also be fairly difficult to test during design and manufacturing verification.
An alternative to analog multi-phase clock generators is therefore desired, which is capable of maintaining phase lock when the reference clock stops, is easy to test, and is relatively insensitive to changes in process, voltage and temperature.